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40V Synchronous Buck Controller
POWER MANAGEMENT Description
SC4612H is a high performance synchronous buck controller that can be configured for a wide range of applications. The SC4612H utilizes synchronous rectified buck topology where high efficiency is the primary consideration. SC4612H can be used over a wide input voltage range with output voltage adjustable within limits set by the duty cycle boundaries. SC4612H comes with a rich set of features such as regulated DRV supply, programmable soft-start, high current gate drivers, shoot through protection, RDS-ON sensing with hiccup over current protection.
SC4612H
Features
u u u u u u u u u u
Wide input voltage range, 4.75V to 40V Internally regulated DRV 1.7A gate drive capability Low side RDS-ON sensing with hiccup OCP Programmable current limit Programmable frequency up to 1.2 MHz Overtemperature protected Pre-bias startup Reference accuracy 1% Available in MLPD-12 4 x 3 and SOIC-14 Pb-free packages. This product is fully WEEE and RoHS compliant Distributed power architectures Telecommunication equipment Servers/work stations Mixed signal applications Base station power management Point of use low voltage high current applications
Applications
u u u u u u
Typical Application Circuit
R1 adj
1 IL IM
U1 S C4612MLP
PHASE 12
D1
C1
2 OSC DH 11
C2
3 SS/E N BST 10
C3
R2 C4
4
EAO
DRV
9
C8 C7 Q1 L1
5
FB
DL
8
+
Q2 C9 C10 C11
+
R3 opt C5
6
VDD
GND
7
Vout
_
Vin
_
Ci n
R5
R4 C6 R6
Revision: August 14, 2008
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SC4612H
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Bias Supply Voltage to GND PHASE to GND DRV, ILIM, DL to GND, BST, DH to PHASE EAO, SS/EN, FB, OSC to GND DRV Source Current (peak) Thermal Resistance Junction to Ambient (MLPD) Thermal Resistance Junction to Case (MLPD) Thermal Resistance Junction to Ambient (SOIC) Thermal Resistance Junction to Case (SOIC) Storage Temperature Range Peak IR Reflow Temperature (10-40s) Lead Temperature (10s), (SOIC-14)
(1) (1)
Symbol VDD VIN
Maximum -0.3 to 45 -2 to +55 -0.3 to 10 -0.3 to +5 100
Units V V V V mA C/W C/W C/W C/W C C C
JA JC JA JC TSTG TIR Reflow TLEAD
45.3 11 115 45 -65 to +150 260 300
All voltages with respect to GND. Positive currents are into, and negative currents are out of the specified terminal. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500ns. Consult Packaging Section of Data sheet for thermal limitations and considerations of packages. Note: (1). ThetaJA is calculated from a package in still air, mounted to a 3" x 4.5", 4 layer FR4PCB with thermal vias (if applicable) per JESD51 standards.
Recommended Operating Conditions
Performance is not guaranteed if the conditions below are exceeded.
Parameter Supply Voltage Range Ambient Temperature Range Junction Temperature Range
Symbol VDD TA TJ
Conditions
Min 5 -40 -40
Typ
Max 40 105 125
Units V
o
C C
o
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SC4612H
POWER MANAGEMENT Electrical Characteristics
Unless otherwise specified: VIN = VDD = 12V, FOSC = 600kHz, TA = TJ = 25C.
Parameter Bias Supply Quiescent Current VDD Undervoltage Lockout Start Threshold UVLO Hysteresis Drive Regulator DRV Load Regulation Oscillator Operation Frequency Range Initial Accuracy (1) Maximum Duty Cycle
Test Conditions
Min
Typ
Max
Units
VDD = 40V, No load, SS/EN = 0
5
7
mA
4.20
4.50 400
4.75
V mV
10V VDD 40V, IOUT 1mA 1mA IOUT 70mA
7.3
7.8
8.3 100
V mV
100 C OSC = 160pF (Ref only) V DD = VDR = 8V; VOUT_NOM = 5V; IOUT = 0A 82 VIN adjust down to VOUT = 0.99 * VOUT _NOM 540 600
1200 660
kHz kHz %
Ramp Peak to Valley (1) Oscillator Charge Current Current Limit (Low Side Rdson) Current Limit Threshold Voltage Error Amplifier Feedback Voltage TJ = 0 to +70C TJ = -40 to +85C TJ = -40 to +125C Input Bias Current Open Loop Gain
(1)
850 VOSC = 1V 90 110
mV A
See Pg. 12 & 13 on OCP
100
mV
0.495 0.492 0.488
0.500 0.500 0.500
0.505 0.508 0.512 200
V V V nA dB MHz A A V/s
FB = 0.5V 60 7 Open Loop, FB = 0V Open Loop, FB = 0.6V 10 900 1100 1
Unity Gain Bandwidth (1) Output Sink Current Output Source Current Slew Rate (1)
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SC4612H
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise specified: VIN = VDD = 12V, FOSC = 600kHz, TA = TJ = 25C.
Parameter SS/EN Disable Threshold Voltage Soft Start Charge Current Soft Start Discharge Current Disable Low to Shut Down (1) Hiccup Hiccup duty cycle Gate Drive Gate Drive On-Resistance (H)(2) Gate Drive On-Resistance (L)(2) DL Source/Sink Peak Current(2) DH Source/Sink Peak Current(2) Output Rise Time(2) Output Fall Time(2) Minimum Non-Overlap (1) Minimum On Time (2) Thermal Shutdown Shutdown Temperature (2) Thermal Shutdown Hysteresis (2)
(1)
Test Conditions
Min
Typ
Max
Units
500 25 1 50
mV A A ns
CSS = 0.1, current limit condition
1
%
ISOURCE = 100mA ISINK = 100mA COUT = 2000pF COUT = 2000pF COUT = 2000pF COUT = 2000pF 1.4 1.4
3 3 1.7 1.7 20 20 30
4 4
A A ns ns ns
110
ns
165 15
C C
Notes: (1) Guaranteed by design. Not production tested. (2) Guaranteed by characterization. (3) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC4612H
POWER MANAGEMENT Pin Configurations
TOP VIEW
ILIM OSC SS/EN EAO FB VDD 1 2 3 4 5 6 12 11 10 9 8 7 PHASE DH BST DRV DL GND
Ordering Information
Part Number(3) SC4612HMLTRT SC4612HSTRT SC4612HEVB(1) Package(2) MLPD-12 4 x 3 -40C to +125C SOIC-14 EVALUATION BOARD Temp. Range (TJ)
(12 Pin MLPD)
Notes: (1) When ordering please specify MLPD or SOIC package. (2) Only available in tape and reel packaging. A reel contains 3000 devices for MLPD package and 2500 for SOIC package.. (3) Pb-free product. This product is fully WEEE and RoHS compliant.
TOP VIEW
NC ILIM OSC SS/EN EAO VDD NC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 PHASE DH BST DRV DL GND FB
(14 Pin SOIC)
Marking Information - MLPD
Top Mark
Marking Information - SOIC
Top Mark
4612H yyww xxxxx
SC4612H yyww xxxxxxxxx
nnnn yyww xxxxx
= Part Number (Example: 1531) = Date Code (Example: 0012) = Semtech Lot No. (Example:E9010)
nnnn = Part Number (Example: SC4612H) yyww =Date Code (Example: 0752) xxxxx = Semtech Lot No. (Example:A01E90101)
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SC4612H
POWER MANAGEMENT Pin Descriptions
Pin # MLPD Pin# SOIC 1, 7 1 2 Pin Name NC ILIM Pin Function No connection. The current limit programing resistor at this pin in conjunction with an internal current source programs the current limit threshold for the low side MOSFET RDS-ON sensing. Once the voltage drop across the bottom MOSFET is larger than the programmed value, current limit condition occurs, and the hiccup current limit protection is activated. Oscillator Frequency set pin. An external capacitor to GND will program the oscillator frequency. See Table 1 "Frequency vs. COSC" to determine oscillator frequency. Soft Start pin. Internal current source connected to a single external capacitor will determine the soft-start duration for the output. Inhibits the chip if pulled down. TSS 4 5 6 7 8 9 5 8 6 9 10 11 EAO FB VDD GND DL DRV CSS X 1.2 ISS
2 3
3 4
OSC SS/EN
Error Amplifier Output. A compensation network is connected from this pin to FB. The inverting input of the error amplifier. Feedback pin is used to sense the output voltage via a resistive divider. Bias supply. Also, VDD pin is internally used to provide the base drive to the internal pass transistor regulating the DRV supply. Ground. Drive Low. Gate drive for bottom MOSFET. DRV supplies the external MOSFETs gate drive and the chips internal circuitry. This pin should be bypassed with a ceramic capacitor to GND. DRV is internally regulated from the external supply connected to VDD. If VDD is below 10V, the supply should be directly connected to the DRV pin. BST signal. Supply for high side driver; can be directly connected to an external supply or to a bootstrap circuit. Drive High. Gate drive for top MOSFET. The return path for the high side gate drive, also used to sense the voltage at the phase node for adaptive gate drive protection and the low-side RDS-ON current sensing. Pad for heatsinking purposes. Connect to ground plane using multiple vias.
10 11 12
12 13 14
BST DH PHASE THERMAL PAD (GND)
X
N/A
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SC4612H
POWER MANAGEMENT Block Diagram
S R
Q
CO_INT BST
EN
S R DRV Q
OTP
DH PHASE
S_MOD + 830mV
S R Q
DL GND
OSC DRV DRV VDD VDD
REG & BG
OSC SPLSE VREF V+ DRV SS_3 OUT VOSC + 12k 0.6V - OVP + OC DETECT SQ R EAO
VREF VREF VSS
FB
ILIM
OC
SOFTSTART SSDN SSLO SSINT SS/EN SS SSHI
S R
Q
S R
Q
S R
Q
SQ R
d
d
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SC4612H
POWER MANAGEMENT Typical Characteristics
Typical Soft Start Current vs Temperature 25 1.5 Typical Error Amp Output Current vs Temperature
1.0
Source; VEAO=0V; VFB=0V
SS Current (uA)
24 IEAO (mA) 23
0.5
0.0
-0.5
Sink; VEAO=1.5V; VFB=0.6V
-1.0 22 -50 0 50 Temperature ( C)
O
100
150
-1.5 -50 0 50 Temperature ( C)
O
100
150
Typical DRV Voltage vs Load Current 8
-40C
Typical UVLO vs Temperature 4.5
VDD Rising
4.4 7
25C
Undervoltage Trip (V)
VDRV (V)
4.3
4.2
6
4.1
125C
VDD Falling
5 0 20 40 60 IDRV (mA) 80 100 120 140
4.0 -50 0 50 Temperature ( C)
O
100
150
Typical VFB vs Temperature 503 104
Typical Oscillator Charge Current vs Temperature
502
102
501 VFB (mV)
VDD=42V
500
IOSC (uA)
VDD=5V
100
98
499 96
498
497 -50 0 50 Temperature ( C)
O
94 100 150 -50 0 50 Temperature ( C)
O
100
150
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SC4612H
POWER MANAGEMENT Typical Characteristics (Cont.)
Typical VDD Quiescent current vs Temperature 5
Start Up from VOUT = 0V
4
VDD=42V
3 Iq (mA)
VDD=12V
2
1
0 -50 0 50 Temperature ( C)
O
100
150
Start Up from VOUT = 2.5V
Start Up from VOUT = 2.5V First DH/DL Pulses
Short Circuit Applied
Steady State Waveforms
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SC4612H
POWER MANAGEMENT Applications Information
INTRODUCTION The SC4612H is a versatile voltage mode synchronous rectified buck PWM convertor, with an input supply (VIN) ranging from 4.5V to 40V designed to control and drive N-channel MOSFETs. The power dissipation is controlled by allowing high speed and integration with the high drive currents to ensure low MOSFET switching loss. The synchronous buck configuration also allows converter sinking current from load without losing output regulation. The internal reference is trimmed to 500mV with 1% accuracy, and the output voltage can be adjusted by an external resistor divider. A fixed oscillator frequency (up to 1.2MHz) can be programmed by an external capacitor for design optimization. Other features of the SC4612H include: Wide input power voltage range (from 4.5V to 40V), low output voltages, externally programmable soft-start, hiccup over current protection, wide duty cycle range, thermal shutdown, and -40 to 125C junction operating temperature range. THEORY OF OPERATION SUPPLIES Two pins (VDD and DRV) are used to power up the SC4612H. If input supply (Vin) is less than 10V, tie DRV and VDD together. This DRV supply should be bypassed with a low ESR 2.2uF (or greater) ceramic capacitor directly at the DRV to GND pins of the SC4612H. The DRV supply also provides the bias for the low and the high side MOSFET gate drive. The maximum rating for DRV supply is 10V and for applications where input supply is below 10V, it should be connected directly to VDD. The internal pass transistor will regulate the DRV from an external supply connected to VDD to produce 7.8V typical at the DRV pin. Soft Start / Shut down The SC4612H performs a "pre-bias" type startup. This ensures that a pre-charged output capacitor will not cause the SC4612H to turn on the bottom FET during
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Cosc, (pF)
startup to discharge it, as a normal synchronous buck controller would do. An external capacitor on the SS/EN pin is used to set the Soft Start duration.
TSS 0.5 * CSS 25 * 10 -6
Startup is inhibited until VDD input reaches the UVLO threshold (typically 4.5V). Once VDD rises above UVLO, the external soft start capacitor begins to charge from an internal 25uA current source. When the SS/EN pin reaches approximately 0.8V, top side switching is enabled. However, a top side pulse will not occur until SS/EN has charged up to the level appropriate for the existing output voltage (a pre bias condition). Once the first top side gate pulse actually occurs, the bottom side driver is enabled and the remainder of the startup is fully synchronous. In the event of an over current during startup, the SC4612H behaves in the same manner as an over current in steady state (see Over Current Protection). Oscillator Frequency Selection The internal oscillator sawtooth signal is generated by charging an external capacitor with a current source of 100A charge current. See Table 1 "Frequency vs. COSC" to determine oscillator frequency. Frequency, vs. COSC
1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 100 200 300 400 500 600 700 800 900 1000 1100 1200
Frequency, (kHz)
Table 1
SC4612H
POWER MANAGEMENT Applications Information (Cont.)
Under Voltage Lock Out Under Voltage Lock Out (UVLO) circuitry senses the VDD through a voltage divider. If this signal falls below 4.5V (typical) with a 400mV hysteresis (typical), the output drivers are disabled. During the thermal shutdown, the output drivers are disabled. OVERCURRENT PROTECTION The SC4612H features low side MOSFET RDS(ON) current sensing and hiccup mode over current protection. The voltage across the bottom FET is sampled approximately 150ns after it is turned on to prevent false tripping due to ringing of the phase node. The internally set over current threshold is 100mV typical. This can be adjusted up or down by connecting a resistor between ILIM and DRV or GND respectively. When programming with an external resistor, threshold set point accuracy will be degraded to 30%. The FET RDS(ON) at temperature will typically be 150% or more of the room temperature value. Allowance should be made for these sources of error when programming a threshold value. When an over current event occurs, the SC4612H immediately disables both gate drives. The SS ramp continues to its final value, if not already there. Once at final value, the SS capacitor is discharged at approximately 1uA until SS low value is reached (approx 0.8V). The SS/ Hiccup cycle will then repeat until the fault condition is removed and the SC4612H starts up normally on the next SS cycle. Gate Drive/Control The SC4612H provides integrated high current drivers for fast switching of large MOSFETs. The higher gate current will reduce switching losses of the larger MOSFETs. The low side gate drive is supplied directly from the DRV. The high side gate drive is bootstraped from the DRV pin. Cross conduction prevention circuitry ensures a non overlapping (30ns typical) gate drive between the top and bottom MOSFETs. This prevents shoot through losses which provides higher efficiency. Typical total minimum off time for the SC4612H is about 30ns. ERROR AMPLIFIER DESIGN The SC4612H is a voltage mode buck controller that utilizes an externally compensated high bandwidth error amplifier
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to regulate the output voltage. The power stage of the synchronous rectified buck converter control-to-output transfer function is as shown below.
1 + sESR C V C IN x G ( s) = VD L V + s2LC S 1+ s R L
where, VIN - Input voltage L - Output inductance ESRC - Output capacitor ESR VS - Peak to peak ramp voltage RL - Load resistance C - Output capacitance
The classical Type III compensation network can be built around the error amplifier as shown below:
C3 C2 R1 + Vref R3 R2 C1
Figure 1. Voltage mode buck converter compensation network. The transfer function of the compensation network is as follows:
s )(1 + Z1 GCOMP (s) = I s (1 + s )(1 + P1 (1 + s ) Z 2 s ) P 2
where,
Z1 = 1 1 1 , Z 2 = , o = R 2C1 (R1 + R 3 )C2 Lout x Cout P1 = 1 , R3C2 P 2 = 1 C1C3 R2 C1 + C3
I =
1 , R1(C1 + C3 )
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SC4612H
POWER MANAGEMENT Applications Information (Cont.)
The design guidelines are as following: 1. Set the loop gain crossover frequency wC for given switching frequency. 2. Place an integrator at the origin to increase DC and low frequency gains. 3. Select wZ1 and wZ2 such that they are placed near wO to dampen peaking; the loop gain should cross 0dB at a rate of -20dB/dec. 4. Cancel wESR with compensation pole wP1 (wP1 = wESR ). 5. Place a high frequency compensation pole wP2 at half the switching frequency to get the maximum attenuation of the switching ripple and the high frequency noise with adequate phase lag at wC.
T
Z1 o
Loop gain T(s) Z2
Gd 0dB
c p1 p2
ESR
Figure 2. Simplified asymptotic diagram of buck power stage and its compensated loop gain.
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SC4612H
POWER MANAGEMENT Application Information (Cont.)
COMPONENT SELECTION: SWITCHING SECTION OUTPUT CAPACITORS - Selection begins with the most critical component. Because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. Output capacitor ESR is therefore one of the most important criteria. The maximum ESR can be simply calculated from: R ESR Vt It The maximum inductor value may be calculated from:
L R ESR C (VIN - V O ) It
Where Vt = Maximum transient voltage excursion I t = Transient current step For example, to meet a 100mV transient limit with a 10A load step, the output capacitor ESR must be less than 10m. To meet this kind of ESR level, there are three available capacitor technologies.
Each Capacitor Technology C (uF) Ceramic SP Cap POS-CAP Low ESR Aluminum 22 220 680 1500 ESR (m) 2-10 7 18 44 Total Qty Rqd. C (uF) 22 220 1360 7500 ESR (m) 2-10 7.0 9.0 8.8
The calculated maximum inductor value assumes 100% duty cycle, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from:
ILRIPPLE = VIN 4 L fOSC
Ripple current allowance will define the minimum permitted inductor value. POWER FETS - The FETs are chosen based on several criteria with probably the most important being power dissipation and power handling capability. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses. a) Conduction losses are simply calculated as:
PCOND = I2 RDS( on ) D O where D = duty cycle VO VIN
1 1 2 5
The choice of which to use is simply a cost/performance issue, with low ESR Aluminum being the cheapest, but taking up the most space. INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above.
b) Switching losses can be estimated by assuming a switching time, If we assume 100ns then:
PSW = IO VIN 100ns TSW
or more generally,
IO VIN ( t r + t f ) fOSC 2 c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume PSW =
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SC4612H
POWER MANAGEMENT Application Information (Cont.)
that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be:
PRR = QRR VIN fOSC
Low Side RDS_ON Current Limit
BOTTOM FET - Bottom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it resulting in very low switching losses. Conduction losses for the FET can be determined by:
PCOND = I2 RDS( on ) (1 - D) O
INPUT CAPACITORS - Since the RMS ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size.
1. Programming resistors Ra and Rb - Not installed:
2.75 V - 100mV 100mV - Vphase = R3 R2
solving for: VPHASE = -100mV, therefore the circuit will trip @ RDS_ON x ILOAD = 100mV 2. To increase trip voltage - install Ra.
Ra = -772 - 20 VPHASE 1 + 10 VPHASE
solving for double the current limit: VPHASE = -200mV. Ra = 768k. 3. To decrease trip voltage - install Rb
Rb = 8 - 20 VPHASE 1 + 10 VPHASE
solving for half the current limit: VPHASE = -50mV. Rb = 18k. NOTE! Allow for tempco and RDS_ON variation of the MOSFET - see "overcurrent protection" information on page 11 in the datasheet.
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SC4612H
POWER MANAGEMENT Application Information (Cont.)
Application Circuit 1: Vin = 24V; Vout = 3.3V @ 20A, Fsw = 500kHz.
+
R1 adj
1 ILIM
C14 470/ 35V U1 SC4612MLP
PHASE 12
C15 470/ 35V
Vin=24V
_
D1 MBR0530
C1 200p
2 OSC DH 11
C2 0. 1 C3 3.9n R2 10k
3
SS/EN
BST
10
C8 0. 1
4 EAO DRV 9
C4 300p R3 10 C5 1
5
FB
DL
8
C7 2. 2
Q1
L1 1.5uH
+
Q2 C9
6
VDD
GND
7
C10 180/4V
C11 180/4V
C12 180/4V
C13 10/6.3V
V out=3.3@20A
_
R5 39.2k R4 6.98k C6 750p R6 887
Fsw =500k H z
Vin=24V, Vout_nom=3.3V, Fsw=500kHz
100% 95% 90% 85% 80% 75% 70% 65% 60% 0 2 4 6 8 10 12 14 16 18 20
Efficiency
Current, (A)
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SC4612H
POWER MANAGEMENT Application Information (Cont.)
Application Circuit 2: Vin = 12V; Vout = 3.3V @ 10A, Fsw = 1MHz
+
R1 adj
1 ILIM
C12 220/ 16V U1 SC4612MLP
PHASE 12
Vin=12V
_
D1 MBR0520
C1 82p
2 OSC DH 11
C2 0. 1 C3 2.7n R2 13.7k
3
SS/EN
BST
10
C8 0. 1
4 EAO DRV 9
C4 1n R3 10 C5 1
5
FB
DL
8
C7 2. 2
Q1
L1 1uH
+
Q2 C9
6
VDD
GND
7
C10 680/4V
C11 10
V out=3.3@10A
_
R5 21.5k R4 3.83k C6 1.2n R6 267
Fsw=1000k Hz
Vin=12V, Vout_nom=3.3V, Fsw=1MHz
100% 95% 90% 85% 80% 75% 70% 65% 60% 0 1 2 3 4 5 Current, (A) 6 7 8 9 10
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SC4612H
POWER MANAGEMENT Application Information (Cont.)
Application Circuit 3: Vin = 5V; Vout = 1.25V @ 12A, Fsw = 1MHz.
+
C12 10 0/6.3V R1 adj
1 ILIM
Vin=5V
_
U1 SC4612MLP
PHASE 12
D1 SD107WS
C1 82p C2 0. 1 C3 1n R2 10k
2
OSC
DH
11
3
SS/EN
BST
10
C8 0. 1
4 EAO DRV 9
C4 33p R3 0 C5 1
5
FB
DL
8
C7 2. 2
Q1
L1 0.47u H
+
Q2 C9
6
VDD
GND
7
C10 100/4V
C11 1
Vout=1.25@12A
_
R5 13.3k R4 8.87k C6 510p R6 649
Fsw=1000k Hz
Vin=5V, Vout_nom=1.25V, Fsw=1MHz
100% 95% 90% 85% 80% 75% 70% 65% 60% 0 1 2 3 4 5 6 7 8 9 10 11 12 13
Efficiency
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SC4612H
POWER MANAGEMENT Application Information (Cont.)
Evaluation Board: Top layer and components view
Bottom Layer:
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SC4612H
POWER MANAGEMENT PCB Layout Guidelines
Careful attention to layout is necessary for successful implementation of the SC4612H PWM controller. High switching currents are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1) The high power section of the circuit should be laid out first. A ground plane should be used. The number and position of ground plane interruptions should not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas; for example, the input capacitor and bottom FET ground. 2) The loop formed by the Input Capacitor(s) (Cin), the Top FET (M1), and the Bottom FET (M2) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically "cleaner" grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3) The connection between the junction of M1, M2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. Also keep the Phase connection to the IC short. Top FET gate charge currents flow in this trace. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible. Fast transient load currents are supplied by Cout only, and therefore, connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC4612H is best placed over a quiet ground plane area. Avoid pulse currents in the Cin, M1, M2 loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the output capacitor(s). If this is not possible, the GND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, M1, M2 loop. Under no circumstances should GND be returned to a ground inside the Cin, M1, M2 loop. 6) Allow adequate heat sinking area for the power components. If multiple layers will be used, provide sufficent vias for heat transfer.
VIN I (Input Capacitor)
Ids (Top Fet) Vphase
I (Inductor)
Vout
+
Vout I (Output Capacitor) +
Ids (Bottom Fet)
Voltage and current waveforms of buck power stage .
(c) 2008 Semtech Corp.
19
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SC4612H
POWER MANAGEMENT Outline Drawing - MLPD - 12
A
PIN1 INDICATOR (LASER MARK) D
B
DIM
E A A1 A2 b D D1 E E1 e L N aaa bbb
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.031 .035 .040 .000 .001 .002 - (.008) .007 .010 .012 .154 .157 .161 .124 .130 .134 .114 .118 .122 .061 .067 .071 .020 BSC .012 .016 .020 12 .003 .004 0.80 0.90 1.00 0.00 0.02 0.05 - (0.20) 0.18 0.25 0.30 3.90 4.00 4.10 3.15 3.30 3.40 2.90 3.00 3.10 1.55 1.70 1.80 0.50 BSC 0.30 0.40 0.50 12 0.08 0.10
A2 A SEATING PLANE A1
aaa C C D1 D1/2
12
E1/2 LxN
N
E1
bxN bbb CAB
e
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Land Pattern - MLPD - 12
DIMENSIONS DIM C G H K P X Y Z INCHES (.114) .087 .067 .138 .020 .012 .028 .142 MILLIMETERS (2.90) 2.20 1.70 3.50 0.50 0.30 0.70 3.60
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
(c) 2008 Semtech Corp.
20
www.semtech.com
SC4612H
POWER MANAGEMENT Outline Drawing - SOIC - 14
A e N
2X
D
DIM
A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.053 .069 .004 .010 .049 .065 .020 .012 .007 .010 .337 .341 .344 .150 .154 .157 .236 BSC .050 BSC .010 .020 .016 .028 .041 (.041) 14 0 8 .004 .010 .008 1.35 1.75 0.25 0.10 1.65 1.25 0.31 0.51 0.25 0.17 8.55 8.65 8.75 3.80 3.90 4.00 6.00 BSC 1.27 BSC 0.25 0.50 0.40 0.72 1.04 (1.04) 14 0 8 0.10 0.25 0.20
E/2 E1 E
ccc C 1 2X N/2 TIPS
2
3 B
D aaa C A2 A SEATING PLANE C bxN bbb A1 C A-B D
h h H GAGE PLANE 0.25 L (L1) DETAIL c
01
SEE DETAIL SIDE VIEW
NOTES: 1.
A
A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AB.
Land Pattern - SOIC - 14
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS MILLIMETERS INCHES
(.205) .118 .050 .024 .087 .291 (5.20) 3.00 1.27 0.60 2.20 7.40
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. REFERENCE IPC-SM-782A, RLP NO. 302A.
2.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
(c) 2008 Semtech Corp. 21 www.semtech.com

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